In conventional DRAM, a sense signal from a memory cell is generated by sharing the charge stored in the memory cell with a pre-charged bit line, and then the voltage of the sense signal is compared to that of a reference voltage. The sense signal on the bit line is interpreted as being in a “low” state or a “high” state to determine a “0” or a “1” digital logic output. The reference voltage level is centered between the expected voltage bands of the “low” state and the “high” state. A comparator compares the reference voltage level to the bit line to interpret the sense signal and output the corresponding digital logic level.
Some types of DRAM, such as embedded DRAM (eDRAM), use single-ended sense schemes to interpret whether a sense signal on a bit line is “high” or “low”. Single-ended sense schemes do not include a reference voltage level for comparison. Instead, the bit line is directly coupled to a sense device (e.g., a sensing inverter) that has a switch-point voltage which varies from the midpoint of the “high” and “low” states of the sense signal. The bit line is pre-charged to a voltage such that when the bit line is coupled with a sense signal, the sense signal pulls the voltage of the bit line above or below the switch-point voltage, which is interpreted by the sense device as a “0” or a “1.”
Ideally, the switch-point voltage of every single-ended sense device in a DRAM would be the same. However, in reality, the switch-point voltage of individual single-ended sense devices can be different due to, for example, manufacturing variations and/or operational parameters (e.g., NFET and PFET Vt, transconductance, temperature, and supply voltage). As such, the output of a particular single-ended sense device can change independently of the voltage level of the bit line. Unlike differential sense schemes, which use a reference voltage level, the switch-point voltage of single-ended sense devices cannot be adjusted. In other words, the ability to center the switch-point voltage on the expected voltage bands of the “low” and “high” states is lost, which makes it difficult to design and test DRAM having single-ended sense devices for high yield, maximum retention, and reliability.
Conventional methods for implementing single-ended sense devices attempt to predict the switch-point voltages. For example, during circuit design, design engineers may estimate the switch point voltages based on parasitic capacitance on bit line structures, the input capacitance of the sense devices, and the leakage incurred on the stored charge in the DRAM cells. These values can be predicted during design of the integrated circuit to calculate a value for the bit line voltage. However, these predictions are approximations that may not be accurate for all DRAMs produced in a batch and, thus, may result in the loss of production yield when the switch-point voltage a particular DRAM is outside an acceptable range.